1. Field of the Invention
The present invention relates generally to the field of data transmission and, more specifically, to managing conflicts on a shared L2 data bus.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that temporarily stores data being used by the various clients. This data may be retrieved from or written to an external memory (referred to herein as Dynamic Random Access Memory or “DRAM”). A memory controller (referred to herein as “DRAM controller”) manages the flow of data being transmitted to or retrieved from the DRAM.
A DRAM typically includes multiple DRAM banks, where each bank is divided into multiple bank pages. A bank page within a DRAM bank needs to be activated before data can be transmitted to or retrieved from that bank page. Only one bank page within a specific DRAM bank can be active at any given clock cycle. After the last data transmission to or data retrieval from a particular bank page is complete, a pre-charge command is transmitted to the DRAM bank, causing the bank page to be closed. Future data transmissions and data retrievals associated with that bank page require the re-activation of that particular bank page. As is well-known, activating and pre-charging bank pages within a DRAM bank are both extremely time consuming operations. Therefore, if either of these two operations is executed too frequently, overall system performance may be severely impacted.
Further, as the need for DRAM operation to become faster increases, the minimum number of data transmissions or data retrievals that need to be executed per bank page activation in order to fully utilize the DRAM bus increases. If the number of data transmissions or data retrievals is less than some minimum threshold number, then clock cycles are wasted on the DRAM bus since data is not transmitted during some clock cycles while the different bank pages are activated. If such a situation occurs too frequently, the overall latency of the system increases due to the excessive number of wasted clock cycles on the DRAM bus.
As the foregoing illustrates, what is needed in the art is an effective mechanism for increasing the number of data transmissions or data retrievals executed when a bank page is activated.